TY - GEN
T1 - 10 GHz throughput FinFET dual-edge triggered flip-flops
AU - Esmaeili, S. E.
AU - Al-Khalili, A. J.
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014/9/17
Y1 - 2014/9/17
N2 - In this paper, we investigate the performance, power consumption, and delay, of four dual-edge triggered FinFET flip-flops; namely: the dual-edge triggered conditional precharge flip-flop (DE-CPFF), the differential dual-edge triggered conditional precharge flip-flop (DE-CPFF-D), the symmetric pulse generator flip-flop (SPGFF), and the dual-edge sense amplifier flip-flop (DE-SAFF). The correct operation of the dualedge FinFET flip-flops was simulated on circuits using Berkeley Short-Channel IGFET Model Class of common Multi-Gate FETs (BSIM-CMG) 30-nm technology. The dual-edge triggered FinFET flip-flops have been simulated at a clock frequency of 5 GHz and a throughput of 10 GHz. Simulation results show correct functionality of the flip-flops under supply voltage variations. Comparison between the flip-flops, show that they have comparable data-to-output delay where the difference between the fastest and slowest flip-flop does not exceed 13 ps. The power consumption of the four flip-flops at different data switching activities was also investigated.
AB - In this paper, we investigate the performance, power consumption, and delay, of four dual-edge triggered FinFET flip-flops; namely: the dual-edge triggered conditional precharge flip-flop (DE-CPFF), the differential dual-edge triggered conditional precharge flip-flop (DE-CPFF-D), the symmetric pulse generator flip-flop (SPGFF), and the dual-edge sense amplifier flip-flop (DE-SAFF). The correct operation of the dualedge FinFET flip-flops was simulated on circuits using Berkeley Short-Channel IGFET Model Class of common Multi-Gate FETs (BSIM-CMG) 30-nm technology. The dual-edge triggered FinFET flip-flops have been simulated at a clock frequency of 5 GHz and a throughput of 10 GHz. Simulation results show correct functionality of the flip-flops under supply voltage variations. Comparison between the flip-flops, show that they have comparable data-to-output delay where the difference between the fastest and slowest flip-flop does not exceed 13 ps. The power consumption of the four flip-flops at different data switching activities was also investigated.
UR - http://www.scopus.com/inward/record.url?scp=84908425650&partnerID=8YFLogxK
U2 - 10.1109/CCECE.2014.6900947
DO - 10.1109/CCECE.2014.6900947
M3 - Conference contribution
T3 - Canadian Conference on Electrical and Computer Engineering
BT - Canadian Conference on Electrical and Computer Engineering
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2014 IEEE 27th Canadian Conference on Electrical and Computer Engineering, CCECE 2014
Y2 - 4 May 2014 through 7 May 2014
ER -