TY - JOUR
T1 - Decreasing the Power-Clock Resonant Signal Central Voltage as a Mean for Power Reduction in Integrated Power and Clock Distribution Networks
AU - Imdoukh, Abeer
AU - Esmaeili, Seyed
N1 - Esmaeili, S. E., & Imdoukh, A. (2021). Decreasing the power-clock resonant signal central voltage as a mean for power reduction in integrated power and clock distribution networks. Indian Journal of Science and Technology, 14(33), 2671–2683. https://doi.org/10.17485/IJST/v14i33.1820
PY - 2021/10/11
Y1 - 2021/10/11
N2 - Background/Objectives: Density, performance, and design complexity of integrated circuits are rapidly increasing specifically in 3-D integration where multi-plane synchronization is required. The power and clock distribution networks consume a large portion of the limited on-chip metal resources. In order to reduce the metal overhead associated with the power, global clock, and local clock distribution networks, the concept of an integrated power and clock distribution network (IPCDN) was investigated and correct functionality of combinational and sequential elements verified. This study discusses potential power savings in IPCDNs achieved by reducing the central voltage at which the signal oscillates. Methods/Statistical analysis: In this paper, an IPCDN with differential power-clock signals centered at half the supply voltage is proposed to further reduce the power consumption. The elements of the proposed scheme including the LC differential power-clock driver, clamping circuit, clock buffer, and voltage doubler have been simulated using Tanner 0.25 um CMOS technology at a frequency of 50 MHz and a supply voltage of 2.5 V. Findings: Simulation results indicate that the proposed scheme achieves 75.32% and 76.47% power reduction in the LC differential powerclock driver and clock buffer, respectively. The effects of process, voltage supply, and temperature (PVT) variations on the proposed scheme were also investigated. Discussion: The IPCDN has a large capacitance and is heavily loaded, thus reducing the central voltage of the resonant sinusoidal signal flowing in this network enables significant reduction in power consumption. Novelty/Applications: The proposed scheme enables power reductions in the LC differential power clock driver and clock buffer. The effects of process, voltage supply, and temperature (PVT) variations on all circuit elements of the proposed scheme was investigated.
AB - Background/Objectives: Density, performance, and design complexity of integrated circuits are rapidly increasing specifically in 3-D integration where multi-plane synchronization is required. The power and clock distribution networks consume a large portion of the limited on-chip metal resources. In order to reduce the metal overhead associated with the power, global clock, and local clock distribution networks, the concept of an integrated power and clock distribution network (IPCDN) was investigated and correct functionality of combinational and sequential elements verified. This study discusses potential power savings in IPCDNs achieved by reducing the central voltage at which the signal oscillates. Methods/Statistical analysis: In this paper, an IPCDN with differential power-clock signals centered at half the supply voltage is proposed to further reduce the power consumption. The elements of the proposed scheme including the LC differential power-clock driver, clamping circuit, clock buffer, and voltage doubler have been simulated using Tanner 0.25 um CMOS technology at a frequency of 50 MHz and a supply voltage of 2.5 V. Findings: Simulation results indicate that the proposed scheme achieves 75.32% and 76.47% power reduction in the LC differential powerclock driver and clock buffer, respectively. The effects of process, voltage supply, and temperature (PVT) variations on the proposed scheme were also investigated. Discussion: The IPCDN has a large capacitance and is heavily loaded, thus reducing the central voltage of the resonant sinusoidal signal flowing in this network enables significant reduction in power consumption. Novelty/Applications: The proposed scheme enables power reductions in the LC differential power clock driver and clock buffer. The effects of process, voltage supply, and temperature (PVT) variations on all circuit elements of the proposed scheme was investigated.
U2 - 10.17485/IJST/v14i33.1820
DO - 10.17485/IJST/v14i33.1820
M3 - Article
VL - 14
SP - 2671
EP - 2683
JO - Indian Journal of Science and Technology
JF - Indian Journal of Science and Technology
IS - 33
M1 - 0974-5645
ER -